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#define | _PACKED __attribute__((packed)) |
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#define | ADS122_NUM_REG 16U |
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#define | ADS122_RESETn_BITOFFSET 7 |
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#define | ADS122_RESETn_MASK (1 << 7) |
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#define | ADS122_AVDD_UV_BITOFFSET 6 |
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#define | ADS122_AVDD_UV_MASK (1 << 6) |
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#define | ADS122_REF_UV_BITOFFSET 5 |
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#define | ADS122_REF_UV_MASK (1 << 5) |
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#define | ADS122_REG_MAP_CRC_FAULT_BITOFFSET 3 |
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#define | ADS122_REG_MAP_CRC_FAULT_MASK (1 << 3) |
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#define | ADS122_MEM_FAULT_BITOFFSET 2 |
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#define | ADS122_MEM_FAULT_MASK (1 << 2) |
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#define | ADS122_REG_WRITE_FAULT_BITOFFSET 1 |
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#define | ADS122_REG_WRITE_FAULT_MASK (1 << 1) |
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#define | ADS122_DRDY_BITOFFSET 0 |
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#define | ADS122_DRDY_MASK (1 << 0) |
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#define | ADS122_CONV_COUNT_BITOFFSET 4 |
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#define | ADS122_CONV_COUNT_MASK (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) |
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#define | ADS122_GPIO3_DAT_IN_BITOFFSET 3 |
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#define | ADS122_GPIO3_DAT_IN_MASK (1 << 3) |
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#define | ADS122_GPIO2_DAT_IN_BITOFFSET 2 |
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#define | ADS122_GPIO2_DAT_IN_MASK (1 << 2) |
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#define | ADS122_GPIO1_DAT_IN_BITOFFSET 1 |
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#define | ADS122_GPIO1_DAT_IN_MASK (1 << 1) |
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#define | ADS122_GPIO0_DAT_IN_BITOFFSET 0 |
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#define | ADS122_GPIO0_DAT_IN_MASK (1 << 0) |
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#define | ADS122_RESET_BITOFFSET 2 |
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#define | ADS122_RESET_MASK (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |
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#define | ADS122_START_BITOFFSET 1 |
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#define | ADS122_START_MASK (1 << 1) |
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#define | ADS122_STOP_BITOFFSET 0 |
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#define | ADS122_STOP_MASK (1 << 0) |
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#define | ADS122_REG_DEVICE_CFG_DEFAULT ((uint8_t)0x04) |
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#define | ADS122_PWDN_BITOFFSET 7 |
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#define | ADS122_PWDN_MASK (1 << 7) |
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#define | ADS122_STBY_MODE_BITOFFSET 6 |
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#define | ADS122_STBY_MODE_MASK (1 << 6) |
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#define | ADS122_BOCS_BITOFFSET 4 |
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#define | ADS122_BOCS_MASK (1 << 5) | (1 << 4) |
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#define | ADS122_CLK_SEL_BITOFFSET 3 |
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#define | ADS122_CLK_SEL_MASK (1 << 3) |
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#define | ADS122_CONV_MODE_BITOFFSET 2 |
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#define | ADS122_CONV_MODE_MASK (1 << 2) |
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#define | ADS122_SPEED_MODE_BITOFFSET 0 |
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#define | ADS122_SPEED_MODE_MASK (1 << 1) | (1 << 0) |
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#define | ADS122_REG_DATA_RATE_CFG_DEFAULT ((uint8_t)0x00) |
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#define | ADS122_DELAY_BITOFFSET 4 |
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#define | ADS122_DELAY_MASK (1 << 7) | (1 << 6) || (1 << 5) || (1 << 4) |
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#define | ADS122_GC_EN_BITOFFSET 3 |
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#define | ADS122_GC_EN_MASK (1 << 3) |
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#define | ADS122_FLTR_OSR_BITOFFSET 0 |
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#define | ADS122_FLTR_OSR_MASK (1 << 2) | (1 << 1) | (1 << 0) |
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#define | ADS122_REG_MUX_CFG_DEFAULT ((uint8_t)0x00) |
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#define | ADS122_AINP_BITOFFSET 4 |
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#define | ADS122_AINP_MASK (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) |
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#define | ADS122_AINN_BITOFFSET 0 |
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#define | ADS122_AINN_MASK (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0) |
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#define | ADS122_REG_GAIN_CFG_DEFAULT ((uint8_t)0x00) |
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#define | ADS122_SYS_MON_BITOFFSET 4 |
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#define | ADS122_SYS_MON_MASK (1 << 6) | (1 << 5) | (1 << 4) |
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#define | ADS122_GAIN_BITOFFSET 0 |
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#define | ADS122_GAIN_MASK (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0) |
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#define | ADS122_REG_REFERENCE_CFG_DEFAULT ((uint8_t)0x00) |
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#define | ADS122_REF_UV_EN_BITOFFSET 7 |
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#define | ADS122_REF_UV_EN_MASK (1 << 7) |
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#define | ADS122_REFP_BUF_EN_BITOFFSET 5 |
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#define | ADS122_REFP_BUF_EN_MASK (1 << 5) |
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#define | ADS122_REFN_BUF_EN_BITOFFSET 4 |
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#define | ADS122_REFN_BUF_EN_MASK (1 << 4) |
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#define | ADS122_REF_VAL_BITOFFSET 2 |
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#define | ADS122_REF_VAL_MASK (1 << 2) |
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#define | ADS122_REF_SEL_BITOFFSET 0 |
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#define | ADS122_REF_SEL_MASK (1 << 1) | (1 << 0) |
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#define | ADS122_REG_DIGITAL_CFG_DEFAULT ((uint8_t)0x00) |
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#define | ADS122_REG_MAP_CRC_EN_BITOFFSET 6 |
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#define | ADS122_REG_MAP_CRC_EN_MASK (1 << 6) |
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#define | ADS122_I2C_CRC_EN_BITOFFSET 5 |
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#define | ADS122_I2C_CRC_EN_MASK (1 << 5) |
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#define | ADS122_STATUS_EN_BITOFFSET 4 |
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#define | ADS122_STATUS_EN_MASK (1 << 4) |
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#define | ADS122_FAULT_PIN_BEHAVIOR_BITOFFSET 3 |
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#define | ADS122_FAULT_PIN_BEHAVIOR_MASK (1 << 3) |
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#define | ADS122_CODING_BITOFFSET 1 |
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#define | ADS122_CODING_MASK (1 << 1) |
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#define | ADS122_REG_GPIO_CFG_DEFAULT ((uint8_t)0x00) |
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#define | ADS122_GPIO3_CFG_BITOFFSET 6 |
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#define | ADS122_GPIO3_CFG_MASK (1 << 7) | (1 << 6) |
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#define | ADS122_GPIO2_CFG_BITOFFSET 4 |
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#define | ADS122_GPIO2_CFG_MASK (1 << 5) | (1 << 4) |
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#define | ADS122_GPIO1_CFG_BITOFFSET 2 |
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#define | ADS122_GPIO1_CFGR_MASK (1 << 3) | (1 << 2) |
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#define | ADS122_GPIO0_CFG_BITOFFSET 0 |
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#define | ADS122_GPIO0_CFG_MASK (1 << 1) | (1 << 0) |
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#define | ADS122_REG_GPIO_DATA_OUTPUT_DEFAULT ((uint8_t)0x00) |
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#define | ADS122_GPIO3_SRC_BITOFFSET 7 |
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#define | ADS122_GPIO3_SRC_MASK (1 << 7) |
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#define | ADS122_GPIO2_SRC_BITOFFSET 6 |
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#define | ADS122_GPIO2_SRC_MASK (1 << 6) |
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#define | ADS122_GPIO3_DAT_OUT_BITOFFSET 3 |
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#define | ADS122_GPIO3_DAT_OUT_MASK (1 << 3) |
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#define | ADS122_GPIO2_DAT_OUT_BITOFFSET 2 |
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#define | ADS122_GPIO2_DAT_OUT_MASK (1 << 2) |
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#define | ADS122_GPIO1_DAT_OUT_BITOFFSET 1 |
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#define | ADS122_GPIO1_DAT_OUT_MASK (1 << 1) |
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#define | ADS122_GPIO0_DAT_OUT_BITOFFSET 0 |
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#define | ADS122_GPIO0_DAT_OUT_MASK (1 << 0) |
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#define | ADS122_REG_IDAC_MAG_CFG_DEFAULT ((uint8_t)0x00) |
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#define | ADS122_I2MAG_BITOFFSET 4 |
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#define | ADS122_I2MAG_MASK (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4) |
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#define | ADS122_I1MAG_BITOFFSET 0 |
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#define | ADS122_I1MAG_MASK (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0) |
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#define | ADS122_IUNIT_Length 4 |
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#define | ADS122_REG_IDAC_MUX_CFG_DEFAULT ((uint8_t)0x10) |
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#define | ADS122_IUNIT_BITOFFSET 7 |
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#define | ADS122_IUNIT_MASK (1 << 7) |
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#define | ADS122_I2MUX_BITOFFSET 4 |
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#define | ADS122_I2MUX_MASK (1 << 6) | (1 << 5) | (1 << 4) |
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#define | ADS122_I1MUX_BITOFFSET 0 |
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#define | ADS122_I1MUX_MASK (1 << 2) | (1 << 1) | (1 << 0) |
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#define | ADS122_REG_REG_MAP_CRC_DEFAULT ((uint8_t)0x00) |
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ADS122C14ITER Current Sensing library.